When the chip size package (CSP) having a through silicon via (TSV) in its structure proposed in Patent Literature 1 was mounted to a substrate and subjected to a temperature cycle test, an insulating film (such as SiO and SiN) that is a layer under RDL_CU sometimes cracked. This is because SiO and SiN have a coefficient of thermal expansion (CTE) that is 1 to 2 digits smaller than materials around SiO and SiN, such that temperature cycle causes a large stress to be generated.
Specifically, the CTE of each material is 17 ppm for Cu, 0.6 ppm for SiO, 1.0 ppm for SiN, 3.2 ppm for Si, 55 ppm for SM, 31 ppm for solder, and 15 to 20 ppm for a substrate. The insulating film is subjected to both a stress caused by the CTE difference (16 ppm) from Cu and a stress caused by the CTE difference (2.6 ppm) from Si at the same time.
As a countermeasure to this, Patent Literature 2 proposes a method of setting the CTE of the insulating film between Si and metal.